Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Help needed in VHDL Testbench

Hi all, I have written the testbench file in such a manner that I need to perform updowncounting and downcounting based on the value of dir_s. But the problem is, when I execute the code, the di...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hello all,

Once again I have a small clarification to be done regarding testbench. I have written a testbench in which I have used a signal say "XXX_s". Now I use the same signal XXX_s in another source code say "YYY.vhd" by port mapping it. However, I need to again use the same signal, XXX_s for the testbench file that I have written for the source file YYY.vhd. How can I do so?? Thanks in advance