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Altera_Forum's avatar
Altera_Forum
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17 years ago

"Error: Cannot hold value outside clock edge" ?

Hello,

I am trying to compile a VHDL code written by another person. I am getting this error for a number of signals.

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Error (10818): Can't infer register for "S_PLLValid" at DeviceControl.vhd(67) because it does not hold its value outside the clock edge

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The qu(at)rtus Help file apparently does not provide any details on this error.

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Fix the problem identified by the message text. A future version of the qu(at)rtus II software will provide more extensive Help for this error message.

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Can anyone help what the reason is and how can the error be corrected?

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You should check all assignments to the signals marked in the error message. You'll usually find constructs that aren't synthesizable VHDL code, e. g. an asynchronus assignment acting in parallel to a clock synchronous assignment within the same process.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    an asynchronus assignment acting in parallel to a clock synchronous assignment within the same process

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    I think this IS the problem.. Here is the relevant part of the code 

    process(Reset,Clock,RS232InInt,PLLValid )
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elsif(PLLValid'Event and PLLValid='1') then
		 I_PLLOutput<=CONV_INTEGER(PLL);
		 S_PLLValid<='1';
	  elsif(S_PLLValid='1') then
		S_PLLValid<='0';

    I tried to put the signals menioned in the error in the sensitivity list but that did not work. How do I change the code ?

    Thanks !
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    try:

    if(Clock'Event and Clock='1') then

    if(PLLValid='1')then

    I_PLLOutput<=CONV_INTEGER(PLL);

    S_PLLValid<='1';

    elsif(S_PLLValid='1') then

    S_PLLValid<= not S_PLLValid;
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Also, the present code was synthesized on a Xilinx Spartan II FPGA. I am trying it on a Altera Cyclone device which gives error. So its not a VHDL language error but a choice of compiler and the corresponding language construct ?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

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    So its not a VHDL language error...

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    You could have a language error even in code that can be synthesized by some tools. Synthesis tools vary in how much latitude they give for certain things that technically are not legal according to the language standard.

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    ...but a choice of compiler and the corresponding language construct ?

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    Code could be legal according to the standard but still not written in a good way for synthesis purposes. Following the recommended coding styles (most being applicable to all synthesis tools and some potentially being specific to a tool) avoids this situation.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    I tried to put the signals menioned in the error in the sensitivity list but that did not work.

    --- Quote End ---

    The Quartus handbook chapter I referred you to through the other thread has several register examples. They all have only clock and asynchronous inputs like reset in the sensitivity list.

    The sensitivity list in the code you showed has something called "Clock" and also PLLValid, which is used in "PLLValid'Event and PLLValid='1'". PLLValid appears to be used as a clock. You should have only one clock in a process. This appears to be the problem markman was trying to solve with the suggested code change.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks for the replies.

    Another error is when I compile 

    elsif (S_ReceiveParametersFromRS232='1' and RS232InInt'Event and RS232InInt='0' ) then

    I get the errors :

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    Error (10397): VHDL Event Expression error at ddfsControl.vhd(78): can't form clock edge from S'EVENT by combining it with an expression that depends on a signal besides S

    Error (10658): VHDL Operator error at ddfsControl.vhd(78): failed to evaluate call to operator ""and""

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    where apparently Quartus does not allow three signals 'and' together.

    I will go through the coding style guidelines chapter. However, the real challenge lies in re-writing the code.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I again wonder if you have more than one clock in the process. Your elsif line is checking for the falling edge of RS232InInt, making that signal be a clock, but your first error message is about trying to use "S" as a clock.

    The register examples in the coding guidelines have nothing else ANDed in the "if" that does the clock edge detection.

    Another place for code examples is in the Quartus text editor at "Edit --> Insert Template". There are full designs containing registers, and there are multiple register examples in the "Insert Template" dialog box at "VHDL --> Logic --> Registers".
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Basically, the original author of these code had no concept of synchronous logic, to my opinion. There are edge sensitive expressions for various signals, mixed with level sensitive ones. We see now, that some constructs are not accepted by quartus, cause they are incompatible with the used synthesis rules. They may be rewritten easily, but that's probably only the tip of the iceberg. There's a high likelihood that you get occasional violation of timing requirements, resulting in unexpected logical behaviour. So, when rewriting the code, you should give it a more synchronous behaviour, as far as possible.

    In the example 

    elsif (S_ReceiveParametersFromRS232='1' and RS232InInt'Event and RS232InInt='0' ) then

    a possible solution can't be given without knowing the other conditional expressions combined with the shown part. It may be sufficient to move the S_ReceiveParametersFromRS232='1' down by one level. A synchronous solution would se a clock'event as outermost level rather than RS232InInt'Event, as markman suggested in a different case. A synchronous edge detection instead of RS232InInt'Event may be necessary then. It looks more complex a first sight, but gives clearly defined behaviour.