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Altera_Forum
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17 years ago

"Error: Cannot hold value outside clock edge" ?

Hello, I am trying to compile a VHDL code written by another person. I am getting this error for a number of signals. --- Quote Start --- Error (10818): Can't infer register fo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Also, the present code was synthesized on a Xilinx Spartan II FPGA. I am trying it on a Altera Cyclone device which gives error. So its not a VHDL language error but a choice of compiler and the corresponding language construct ?