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So its not a VHDL language error...
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You could have a language error even in code that can be synthesized by some tools. Synthesis tools vary in how much latitude they give for certain things that technically are not legal according to the language standard.
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...but a choice of compiler and the corresponding language construct ?
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Code could be legal according to the standard but still not written in a good way for synthesis purposes. Following the recommended coding styles (most being applicable to all synthesis tools and some potentially being specific to a tool) avoids this situation.
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