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Altera_Forum
Honored Contributor
17 years agoThanks for the replies.
Another error is when I compileelsif (S_ReceiveParametersFromRS232='1' and RS232InInt'Event and RS232InInt='0' ) then I get the errors : --- Quote Start --- Error (10397): VHDL Event Expression error at ddfsControl.vhd(78): can't form clock edge from S'EVENT by combining it with an expression that depends on a signal besides S Error (10658): VHDL Operator error at ddfsControl.vhd(78): failed to evaluate call to operator ""and"" --- Quote End --- where apparently Quartus does not allow three signals 'and' together. I will go through the coding style guidelines chapter. However, the real challenge lies in re-writing the code.