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Altera_Forum's avatar
Altera_Forum
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17 years ago

"Error: Cannot hold value outside clock edge" ?

Hello,

I am trying to compile a VHDL code written by another person. I am getting this error for a number of signals.

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Error (10818): Can't infer register for "S_PLLValid" at DeviceControl.vhd(67) because it does not hold its value outside the clock edge

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The qu(at)rtus Help file apparently does not provide any details on this error.

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Fix the problem identified by the message text. A future version of the qu(at)rtus II software will provide more extensive Help for this error message.

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Can anyone help what the reason is and how can the error be corrected?

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Just to summarize some basic facts that were essentially discussed by other posters:

    The initial code doesn't describe a valid register. You can't have an else or elsif condition that follows a rising_edge(clk) or (clk'event and clk = '1') if you want to synthesize the code. It basically says, "if there wasn't a clock edge..."

    Your second error occurs because AND is left associative in VHDL, so you wrote (A = '1' and B'EVENT) and B = '1'. The B'event must be combined with a level test involving only B to form a clock edge. You should use rising_edge(clk) anyway. QIS is smart enough to synthesize (rising_edge(clk) and enable = '1') as a clock edge with an enable condition. You don't necessarily need to use a nested if statement.

    Josh
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

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    QIS is smart enough to...

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    For those who don't know the acronym, "QIS" is "Quartus II integrated synthesis".