"Error: Cannot hold value outside clock edge" ?

Just to summarize some basic facts that were essentially discussed by other posters:

The initial code doesn't describe a valid register. You can't have an else or elsif condition that follows a rising_edge(clk) or (clk'event and clk = '1') if you want to synthesize the code. It basically says, "if there wasn't a clock edge..."

Your second error occurs because AND is left associative in VHDL, so you wrote (A = '1' and B'EVENT) and B = '1'. The B'event must be combined with a level test involving only B to form a clock edge. You should use rising_edge(clk) anyway. QIS is smart enough to synthesize (rising_edge(clk) and enable = '1') as a clock edge with an enable condition. You don't necessarily need to use a nested if statement.

Josh