Forum Discussion
Altera_Forum
Honored Contributor
17 years agoBasically, the original author of these code had no concept of synchronous logic, to my opinion. There are edge sensitive expressions for various signals, mixed with level sensitive ones. We see now, that some constructs are not accepted by quartus, cause they are incompatible with the used synthesis rules. They may be rewritten easily, but that's probably only the tip of the iceberg. There's a high likelihood that you get occasional violation of timing requirements, resulting in unexpected logical behaviour. So, when rewriting the code, you should give it a more synchronous behaviour, as far as possible.
In the exampleelsif (S_ReceiveParametersFromRS232='1' and RS232InInt'Event and RS232InInt='0' ) then a possible solution can't be given without knowing the other conditional expressions combined with the shown part. It may be sufficient to move the S_ReceiveParametersFromRS232='1' down by one level. A synchronous solution would se a clock'event as outermost level rather than RS232InInt'Event, as markman suggested in a different case. A synchronous edge detection instead of RS232InInt'Event may be necessary then. It looks more complex a first sight, but gives clearly defined behaviour.