Error (10028): Can't resolve multiple constant drivers for net <name> at <??>

All, I figured it out.

// Verilog learning example
module SRAM_Read_Write_Sync ( nrst, Writeclk, Readclk, EQ, write_addr, read_addr);
	input nrst, Writeclk, Readclk;
	output EQ;
	output  write_addr;
	output  read_addr;
	// Declare the address counters as 9-bit counters
	reg  write_addr;
	reg  read_addr;
	reg EQ;
	
	// increment Write address or Read address or do a reset
	always @ (posedge Writeclk or posedge Readclk or negedge nrst)
	begin
		if (!nrst)
			begin
				write_addr = 0;
				read_addr = 0;
			end
		else if (Writeclk)
				write_addr = write_addr + 1;
		else if (Readclk)
				read_addr = read_addr + 1;
	end
	
	always @ (posedge Readclk)
	begin
		if (read_addr == write_addr)
			EQ = 1'b1;
		else
			EQ = 1'b0;
	end
endmodule

Be aware that this design is likely to have problems as you are reading the write_address with the readclk, as you may violate the setup and hold time of the write_addr when reading causing metastability - look into safe clock domain crossing techniques.

Ok, I see your point... and that would definitely come back and bite me sooner or later... but the following code gives me the same Error 10028, so how do I:

// Verilog learning example
module SRAM_Read_Write_Sync_Verilog ( nrst, Writeclk, Readclk, EQ, write_addr, read_addr);
	input nrst, Writeclk, Readclk;
	output EQ;
	output  write_addr;
	output  read_addr;
	// Declare the address counters as 9-bit counters
	reg  write_addr;
	reg  read_addr;
	reg EQ;
	
	// increment Write address or Read address or do a reset
	always @ (negedge nrst)
	begin
		if (!nrst)
			begin
				write_addr <= 0;  // non-blocking
				read_addr <= 0;   // non-blocking
			end
	end
	
	always @ (posedge Writeclk)
	begin
		write_addr = write_addr + 1;
	end
	
	always @ (posedge Readclk)
	begin
		read_addr = read_addr + 1;
	end
endmodule

The reset must be in the same always block as the clock. You're actually not checking for a negative edge of reset - you're waiting for when the reset is low in real hardwarfe - the negedge is a quirk of verilog and the way it is event driven.

always @(posedge Writeclk or negedge nrst)
begin
  if(!nrst) write_addr <= 0;
  else    write_addr <= write_addr + 1;
end
always @(posedge readclk or negedge nrst) begin
  if(!nrst) read_addr <= 0;
  else read_addr <= read_addr + 1;
end

AHH-HA... I never thought of it that way..

Keith -

// Verilog learning example
module SRAM_Read_Write_Sync ( nrst, Writeclk, Readclk, EQ, write_addr, read_addr);
    input nrst, Writeclk, Readclk;
    output EQ;
    output  write_addr;
    output  read_addr;
    // Declare the address counters as 9-bit counters
    reg  write_addr;
    reg  read_addr;
    reg EQ;
    
    // increment Write address or do a reset
    always @ (posedge Writeclk or negedge nrst)
    begin
        if (!nrst)
            write_addr <= 9'h0;
        else // Unlike VHDL, you don't need to check for Writeclk high here.
            write_addr <= write_addr + 1;
    end
    // increment Read address or do a reset
    always @ (posedge Readclk or negedge nrst)
    begin
        if (!nrst)
            read_addr <= 9'h0;
        else // Unlike VHDL, you don't need to check for Readclk high here.
            read_addr <= read_addr + 1;
    end
// read_addr and write_addr are generated from different clocks so
// you probably don't want to compare them directly in one clock domain.
// Maybe just do a combinational compare (not clocked).
    always @*
    begin
        if (read_addr == write_addr)
            EQ = 1'b1;
        else
            EQ = 1'b0;
    end
endmodule

Thanks for the info rsefton. I see you set write_addr <= 9'h0.... why would you prefer that over write_addr <= 0?

Comparing both addresses asynchronously is potentially worse than in a clock domain as it will be very glitchy, especially as you're using a count and not a grey code.

Keith -

OK, now I am trying to expand on the mess I've made. Now I want to do some control with the EQ signal, (either in a clocked or unclocked domain). I am wanting to reset the read address under certain conditions,.... make the read address=write address.... and once again.... I get the (multiple constant drivers....) so it has to be back in the always @ portion. There is getting to be quite a few ORs in it, just so that I can change my read_address.