Error (10028): Can't resolve multiple constant drivers for net <name> at <??>

All, I figured it out.

Following is code that seems to compile, don't know about the EQ yet, but I think I figured a way to reset my counters and increment my counters.

// Verilog learning example
module SRAM_Read_Write_Sync ( nrst, Writeclk, Readclk, EQ, write_addr, read_addr);
	input nrst, Writeclk, Readclk;
	output EQ;
	output  write_addr;
	output  read_addr;
	// Declare the address counters as 9-bit counters
	reg  write_addr;
	reg  read_addr;
	reg EQ;
	
	// increment Write address or Read address or do a reset
	always @ (posedge Writeclk or posedge Readclk or negedge nrst)
	begin
		if (!nrst)
			begin
				write_addr = 0;
				read_addr = 0;
			end
		else if (Writeclk)
				write_addr = write_addr + 1;
		else if (Readclk)
				read_addr = read_addr + 1;
	end
	
	always @ (posedge Readclk)
	begin
		if (read_addr == write_addr)
			EQ = 1'b1;
		else
			EQ = 1'b0;
	end
endmodule

So I needed to add all 3 checks in the first "ALWAYS" then check for active LO (!nrst) to reset the counters. Then complete the other edge clocks to increment the appropriate address_counter. Then start another "ALWAYS" and start expanding from here with more behavior!!

Thanks all,

Keith