Error (10028): Can't resolve multiple constant drivers for net <name> at <??>

Keith -

There's a difference between code that is legal verilog and will compile without errors in a simulator, and code that will synthesize to hardware, which is usually the ultimate goal unless you're just trying to model behavior in simulation. Your second post has an always block that is sensitive to the rising edge of two different clocks. This doesn't make much sense even for modeling, and it would definitely not synthesize. This might work better:

// Verilog learning example
module SRAM_Read_Write_Sync ( nrst, Writeclk, Readclk, EQ, write_addr, read_addr);
    input nrst, Writeclk, Readclk;
    output EQ;
    output  write_addr;
    output  read_addr;
    // Declare the address counters as 9-bit counters
    reg  write_addr;
    reg  read_addr;
    reg EQ;
    
    // increment Write address or do a reset
    always @ (posedge Writeclk or negedge nrst)
    begin
        if (!nrst)
            write_addr <= 9'h0;
        else // Unlike VHDL, you don't need to check for Writeclk high here.
            write_addr <= write_addr + 1;
    end
    // increment Read address or do a reset
    always @ (posedge Readclk or negedge nrst)
    begin
        if (!nrst)
            read_addr <= 9'h0;
        else // Unlike VHDL, you don't need to check for Readclk high here.
            read_addr <= read_addr + 1;
    end
// read_addr and write_addr are generated from different clocks so
// you probably don't want to compare them directly in one clock domain.
// Maybe just do a combinational compare (not clocked).
    always @*
    begin
        if (read_addr == write_addr)
            EQ = 1'b1;
        else
            EQ = 1'b0;
    end
endmodule