Honored Contributor
Honored ContributorOK, now I am trying to expand on the mess I've made. Now I want to do some control with the EQ signal, (either in a clocked or unclocked domain). I am wanting to reset the read address under certain conditions,.... make the read address=write address.... and once again.... I get the (multiple constant drivers....) so it has to be back in the always @ portion. There is getting to be quite a few ORs in it, just so that I can change my read_address.
Example: always @(posedge Readclk or negedge nrst or negedge Read_RST or posedge Read_EQ_Write or negedge EQ) and then a ton of if () else if () else if () else.... Is this correct or am I using the proper technique here or is there some other statement I should be using? I know what I want to do schematically (mostly) but wanting to try using Verilog at this project. Thanks again, Keith
