Error (10028): Can't resolve multiple constant drivers for net <name> at <??>

Keith -

In verilog integers are always 32 bits wide, so when you assign 0 (32 bits) to write_addr (9 bits) you'll always get a synthesis warning about the size mismatch. It can be safely ignored, but assigning the size correctly will eliminate that warning.

I always try to be explicit with size in reset assignments, partly because it shows you clearly the size of the variable you're resetting (so you don't have to go up to the declaration to find out). Kind of a self-documentation practice. But it has the side-benefit of reducing the number of synthesis warnings, which can get into the many thousands for a large design. On the other hand, when I code counters (counter <= counter + 1) I'm almost never explicit about the size just because I like the look of "counter + 1" better than "counter + 9'h1".

To each his own. Most of us are creatures of habit, some good some bad!

In the early days of FPGA/CPLD design I would try to eliminate all compile warnings, and back then it was usually possible. But now with rtl design and IP used everywhere it's virtually impossible to eliminate all warnings and I don't even try. But I always review the synthesis, fitter, and timing reports.

Bob