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Altera_Forum
Honored Contributor
Honored ContributorError (10028): Can't resolve multiple constant drivers for net <name> at <??>
All, Here is one of my Verilog trial-learning code: ============================================================== // Verilog learning example
module SRAM_Read_Write_Sync ( nrst, Writeclk, ...
Altera_ForumHonored Contributor
Honored ContributorBe aware that this design is likely to have problems as you are reading the write_address with the readclk, as you may violate the setup and hold time of the write_addr when reading causing metastability - look into safe clock domain crossing techniques.
I would also be wary of putting both read and write clock in the same always block. there are several issues: 1. You may accidentally put a variable in both clocks, which is not supported in an FPGA 2. In a simulation, in your code, if the read and write clocks are exactly aligned then only the write_addr will be incremented (as you have given precedence to the writeclk over the readclk) 3. It can be confusing for others.
