Error (10028): Can't resolve multiple constant drivers for net <name> at <??>

Ok, I see your point... and that would definitely come back and bite me sooner or later... but the following code gives me the same Error 10028, so how do I:

1) check for a negative edge on nrst to reset my counters

2) increment my 9-bit counters on their appropriate rising clock edges

I've been trying to go through several tutorials and examples and I thought I understood some of it, but.....

What/where can I find what is being meant by the "multiple constant drivers for ?????"

As you can see I am very "green" to Verilog programming.. Hard for me to see the "hardware behavior picture" since I usually do schematic entry....

// Verilog learning example
module SRAM_Read_Write_Sync_Verilog ( nrst, Writeclk, Readclk, EQ, write_addr, read_addr);
	input nrst, Writeclk, Readclk;
	output EQ;
	output  write_addr;
	output  read_addr;
	// Declare the address counters as 9-bit counters
	reg  write_addr;
	reg  read_addr;
	reg EQ;
	
	// increment Write address or Read address or do a reset
	always @ (negedge nrst)
	begin
		if (!nrst)
			begin
				write_addr <= 0;  // non-blocking
				read_addr <= 0;   // non-blocking
			end
	end
	
	always @ (posedge Writeclk)
	begin
		write_addr = write_addr + 1;
	end
	
	always @ (posedge Readclk)
	begin
		read_addr = read_addr + 1;
	end
endmodule

Thanks again,

Keith