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Altera_Forum's avatar
Altera_Forum
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9 years ago

Error (10028): Can't resolve multiple constant drivers for net <name> at <??>

All, Here is one of my Verilog trial-learning code: ============================================================== // Verilog learning example module SRAM_Read_Write_Sync ( nrst, Writeclk, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

The reset must be in the same always block as the clock. You're actually not checking for a negative edge of reset - you're waiting for when the reset is low in real hardwarfe - the negedge is a quirk of verilog and the way it is event driven. 


always @(posedge Writeclk or negedge nrst)
begin
  if(!nrst) write_addr <= 0;
  else    write_addr <= write_addr + 1;
end
always @(posedge readclk or negedge nrst) begin
  if(!nrst) read_addr <= 0;
  else read_addr <= read_addr + 1;
end