Dynamic delay for LVDS inputs on a Cyclone 3

I don't quite understand you. If you mean you are receiving 8 independant serial DDR channels each with its clock then each channel can be passed to your system clock domain using one dc fifo per channel. Then you can do your bit slipping search.

If you don't have sufficient available PLL outputs in your design, I fear, logic delay chains must be actually considered for the design. It's always an option, if no other solution is available, but I won't expect Timequest being able to calculate a variable delay, as you intend it.

I forgot to mention, that the LE delay topic is "hidden" in the Random and Pseudorandom Function chapter of the cookbook. It's clear however, that LE delay chains can be made understandable for Quartus through synthesis attributes, and that a range of 2.5 ns is pretty feasible. You can't expect uniform delay steps, because routing delays and the LAB granularity affects the result. Also type variation and temperature dependance of delays should be considered. If your board is facing large temperature changes during operation, a repeated phase calibration may be required.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY configurable_phase_delay IS GENERIC ( CONF_NR_OF_DELAYS : NATURAL := 32); PORT (
  input     : IN  std_logic;
  output    : OUT std_logic;
  shift_clr : IN  std_logic;
  shift_clk : IN  std_logic;
  shift_up  : IN  std_logic;
  shift_dn  : IN  std_logic
);
END ENTITY;
ARCHITECTURE behav OF configurable_phase_delay IS
SIGNAL delay_register : std_logic_vector(CONF_NR_OF_DELAYS-1 downto 0);
SIGNAL delayed_stages : std_logic_vector(CONF_NR_OF_DELAYS-1 downto 0);
attribute syn_keep: boolean;
attribute syn_keep of delay_register: signal is true;
attribute syn_keep of delayed_stages: signal is true;
BEGIN
output <= delayed_stages(0);
delayed_stages(CONF_NR_OF_DELAYS-1) <= input and delay_register(CONF_NR_OF_DELAYS-1);
delaying : for i in 0 to CONF_NR_OF_DELAYS-2 generate
  delayed_stages(i) <= (input and delay_register(i)) or delayed_stages(i+1);
end generate;
clocking : process(shift_clr, shift_clk) is
begin
  if shift_clr = '1' then
      delay_register   <= (others => '0');
      delay_register(0) <= '1';
  elsif rising_edge(shift_clk) then
    if shift_up = '1' then delay_register <= delay_register(CONF_NR_OF_DELAYS-2 downto 0) & delay_register(CONF_NR_OF_DELAYS-1)          ; end if;
    if shift_dn = '1' then delay_register <= delay_register(0)                            & delay_register(CONF_NR_OF_DELAYS-1 downto 1) ; end if;
  end if;
end process;
END ARCHITECTURE;

You can see from the post-synthesis netlist, that the LEs are implemented as intended.

I have corrected the delay estimation to 0.3 - 0.4 ns based on tests with Cyclone III. I have previously reported the tests about one year ago at Altera Forum.