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Altera_Forum's avatar
Altera_Forum
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15 years ago

Dynamic delay for LVDS inputs on a Cyclone 3

Hello, I have to implement an interface to a sensor chip that delivers its data on several (more than 8) LVDS lines in DDR mode along with an LVDS clock. == Details to the situation == ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You can see from the post-synthesis netlist, that the LEs are implemented as intended.