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If you don't have sufficient available PLL outputs in your design, I fear, logic delay chains must be actually considered for the design. It's always an option, if no other solution is available, but I won't expect Timequest being able to calculate a variable delay, as you intend it.
You can expect about 0.2 to 0.25 ns delay per LE (which would represent an AND/OR combination in your schematic), so about 10 LEs and respective control registers would be needed. Because Cyclone III has 4-input LUTs, two selection inputs would be available.
Basic ideas about implementation of delay chains can be found in the "Advanced Synthesis Cookbook", the topic has been also discussed at Altera forum, e.g. how to tell the synthesis tool not to remove apparently redundant logic elements.
http://www.altera.com/literature/manual/stx_cookbook.pdf --- Quote End ---
Dear FvM:
How did you give the value "0.2 to 0.25 ns delay per LE "? Or do you pint me where to find the comments in altera's datasheet?
Honored Contributor
