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I forgot to mention, that the LE delay topic is "hidden" in the Random and Pseudorandom Function chapter of the cookbook.
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Thanks for direction.
It had taken me some time to find it but in the end I've gotten there. A first mini-project seemed to show, that the fitter doesn't eat up everything.
The magic seems to be a short attribute "syn_keep", which marks the endangered signals.
I'll try to integrate the following in my design and see if reality likes it...
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY configurable_phase_delay IS GENERIC ( CONF_NR_OF_DELAYS : NATURAL := 32); PORT (
input : IN std_logic;
output : OUT std_logic;
shift_clr : IN std_logic;
shift_clk : IN std_logic;
shift_up : IN std_logic;
shift_dn : IN std_logic
);
END ENTITY;
ARCHITECTURE behav OF configurable_phase_delay IS
SIGNAL delay_register : std_logic_vector(CONF_NR_OF_DELAYS-1 downto 0);
SIGNAL delayed_stages : std_logic_vector(CONF_NR_OF_DELAYS-1 downto 0);
attribute syn_keep: boolean;
attribute syn_keep of delay_register: signal is true;
attribute syn_keep of delayed_stages: signal is true;
BEGIN
output <= delayed_stages(0);
delayed_stages(CONF_NR_OF_DELAYS-1) <= input and delay_register(CONF_NR_OF_DELAYS-1);
delaying : for i in 0 to CONF_NR_OF_DELAYS-2 generate
delayed_stages(i) <= (input and delay_register(i)) or delayed_stages(i+1);
end generate;
clocking : process(shift_clr, shift_clk) is
begin
if shift_clr = '1' then
delay_register <= (others => '0');
delay_register(0) <= '1';
elsif rising_edge(shift_clk) then
if shift_up = '1' then delay_register <= delay_register(CONF_NR_OF_DELAYS-2 downto 0) & delay_register(CONF_NR_OF_DELAYS-1) ; end if;
if shift_dn = '1' then delay_register <= delay_register(0) & delay_register(CONF_NR_OF_DELAYS-1 downto 1) ; end if;
end if;
end process;
END ARCHITECTURE;
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