Dynamic delay for LVDS inputs on a Cyclone 3

I don't quite understand you. If you mean you are receiving 8 independant serial DDR channels each with its clock then each channel can be passed to your system clock domain using one dc fifo per channel. Then you can do your bit slipping search.

If your variable delay is due to the board delays then you may get timequest to offset that using static delay per each channel.

I don't see why you need dynamic delay if it is board issue. If the sensor data is so variable from source then I will assume each data has its own clock.

Your own logic of AND OR is a pitfall I believe.