Dynamic delay for LVDS inputs on a Cyclone 3

Hello,

I have to implement an interface to a sensor chip that delivers its data

on several (more than 8) LVDS lines in DDR mode along with an LVDS clock.

== Details to the situation ==

The lines have different phase delays and so I have a hard time to sample

all lines correctly.

The sensor manufacturer explains the handling in a 2 stage training sequence:

* Set the sensor to test mode (where it repeats a static pattern)

* first find the right phase for the data bits by shifting the delay until the sampled data changes and take the middle between two setting where it changes

* second use bit-slipping until the shiftregisters show the right value

The explanation is for Xilinx' Virtex IV devices which seem to have the ability to do the first part without bigger problem - we however are using a Cyclone3 chip and I _have_ bigger problems doing it...

== Already thought about ==

* I've thought about using a separate sample clock for every channel

* I would use up at least 2 PLLs for the solution (that I don't have spare...)

* If I would use dual clock FiFos to do the clock crossing I would loose the context between the LVDS channels

* Timequest can handle input delays but only statically. In the end a delay element with a fixed delay is instantiated.

== The real question ==

I thought, I could implement a structure as in the picture after the diff_input and before the double data rate sampling block.

* The single-ended signal is here fed in at four different places

* It has to pass either 2 or 4 or 6 or 8 gates

* the Delay register which contains only one '1' chooses which path is put out on the output

* You could place many more of these and-or structs in if the delay isn't big enough

input_delay.gif

* Do you think, this could work?

* Will the fitter try to make all paths synchronous again - one of the things I fear?

* Can I use Timequest to

*** make my plans clear (to the fitter)?

*** analyse if it works?

* The data is coming in with 200MHz DDR - is a little bit logic like some "and"s and "or"s able to insert enough delay for 2.5ns delay (max)

Thanks for your patience reading all this.

I hope, I haven't forgotten the important parts and you have gotten a clear view of the problem.

Since I haven't found any usable information to this topic yet, I'm curious to see if there is a good way of doing this.

The sketched solution might be totally bogus - If you feel like it, please tell me so.

And if you know a good / better way of realizing an dynamic delay I'm happy to abandon this strange and-or-scheme.

Best regards,

Roman