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Altera_Forum's avatar
Altera_Forum
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15 years ago

Dynamic delay for LVDS inputs on a Cyclone 3

Hello, I have to implement an interface to a sensor chip that delivers its data on several (more than 8) LVDS lines in DDR mode along with an LVDS clock. == Details to the situation == ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I didn't tell about a datasheet parameter. It's a typical and average value, comprised of LUT and routing delay. You'll find individual "micro-timing" parameters in the device handbooks and delay estimation in timing analysis.

But as already stated, the logic cell delay is also depending on PVT variations, a rnage of about 1:2 can be expected. Thus I wonder, what kind of specification you are looking for?