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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Dynamic delay for LVDS inputs on a Cyclone 3

Hello, I have to implement an interface to a sensor chip that delivers its data on several (more than 8) LVDS lines in DDR mode along with an LVDS clock. == Details to the situation == ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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I have corrected the delay estimation to 0.3 - 0.4 ns based on tests with Cyclone III. I have previously reported the tests about one year ago at Altera Forum.

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it seems altera doesn't provide this parameter in their devices' datasheet. i don't find it when try to check all the datasheet.