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I don't quite understand you. If you mean you are receiving 8 independant serial DDR channels each with its clock
I don't see why you need dynamic delay if it is board issue. If the sensor data is so variable from source then I will assume each data has its own clock.
Your own logic of AND OR is a pitfall I believe.
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Hi,
sadly, I have just one clock and the 8 LVDS channels differ in phase to one another.
The delay between the channels is due to the sensor - no board delay and it seems to change over different operating setting (SPI settings inside the sensor) - I have done successfull trainings with one setting while another fails ...
The AND OR thing _is_ a pitfall since I have thought about it once more and
Input AND (not(DelayReg(0) or DelayReg(1) or DelayReg(2) or DelayReg(3))
would be an equivalent simplification when you "ignored" the timing.
=> The fitter wouldn't leave anything of it.
Honored Contributor
