Detecting preamble

What line is causing the syntax error?

I already see several problems in your code.

You can't define variables in a package declaration (you should be able to define signals though). Functions can't assign values to signals or variables outside themselves, you could use procedures for that. Variables are reinitialized at each function call, you can't keep a value from one call to another. And you don't call any of the functions, so nothing will be synthesized.

I recommend instead of all those functions to put all your code in a single process. Use a cycle counter and decode your data from there.

Thanks for giving me a direction. As per your suggestion I used a Process as follows:

library ieee;

use ieee.std_logic_1164.all;

--declaring global variables

package share is

type input_values1 is array(0 to 25) of integer;

type amplitudearray1 is array(0 to 905) of integer;

type interval_values1 is array(0 to 18) of integer;

end package share;

library ieee;

use IEEE.std_logic_1164.all;

use work.share.all;

entity preamble_det is

Port(clk: in std_logic;

amplitudearray: in amplitudearray1;

interval_values: out interval_values1);

end preamble_det;

architecture behave of preamble_det is

constant nrofcycle_perinterval: integer :=25;

constant nrofinterval: integer :=18;

constant nrofallcycle_max: integer :=nrofcycle_perinterval*nrofinterval;

begin

process(clk)

variable contents_values: amplitudearray1;

variable input_values: input_values1;

variable n : integer;

variable n1 : integer;

variable nrofcycle : integer := 0;

variable cycle : integer := 0;

variable sum_a : integer := 0;

variable sum_b : integer := 0;

variable contents_I1 : integer;

variable allcycles : integer := 0;

variable i : integer;

begin

if (rising_edge(clk)) then

for n in 1 to 905 loop

if ((cycle+1) > nrofcycle_perinterval) then

cycle:= 1;

else

cycle:=cycle+1;

end if;

nrofcycle:=nrofcycle+1;

sum_a:=sum_a+(amplitudearray(n));

if (nrofcycle>nrofcycle_perinterval) then

sum_b:=sum_b+input_values(cycle);

contents_I1:=sum_a-sum_b;

if ((allcycles+1) > nrofallcycle_max) then

allcycles:= 1;

else

allcycles:= (allcycles+1);

end if;

contents_values (allcycles):=contents_I1;

if(nrofcycle>nrofallcycle_max) then

for n1 in 1 to 18 loop

if ((allcycles-(nrofcycle_perinterval*(n1-1)))<1) then

i:= (allcycles-(nrofcycle_perinterval*(n1-1))+nrofallcycle_max);

else

i:= allcycles-(nrofcycle_perinterval*(n1-1));

end if;

interval_values (n1) <= contents_values (i);

end loop;

end if;

end if;

input_values(cycle):=amplitudearray(n);

end loop;

end if;

end process;

end behave;

During running this program either Quartus II 11.0 becomes hang or I got the following errors::

Error: Out of memory in module quartus_map.exe (4097 megabytes used) while running 32-bit Quartus II on a 64-bit OS platform. Please use the 64-bit Quartus II to increase memory capacity.

Error: Current module quartus_map ended unexpectedly

Is there any way to reduce the memory? I checked the same Program in "C programming" where it works fine using 5 functions for each stage.

I read that ""Signal represents interconnection wires that connect component

instantiation ports together whereas Variable is used for local storage of temporary data and visible only inside a process"". But here I am still unable to decide which one I should take as a variable and which one as signal.

Further help will be highly appreciated.

Picking a small snippet of your code

for n in 1 to 905 loop 
if ((cycle+1) > nrofcycle_perinterval) then
cycle:= 1;
else
cycle:=cycle+1;
end if; 
nrofcycle:=nrofcycle+1;
sum_a:=sum_a+(amplitudearray(n));

Do you understand what a VHDL iteration (e.g. a for loop) does? It constructs parallel logic. You have several unconstraint integer (32-bit each) arithmetic expressions inside the loop, as rough estimation the loop will consume at least several 100k logic cells. Can you imagine that Quartus doesn't like it? In any case, the design won't fit any reasonable FPGA size.

Simple conclusion, consider what you want to achieve, redesign your code to execute sequentially or find a different way to make it FPGA compatible.

Hello FvM,

I tried different way using Functions as follows::

library ieee;

use ieee.std_logic_1164.all;

--making global variables as these variables are used by 5 functions in my case

package share is

variable nrofcycle : integer := 0;

variable cycle : integer := 0;

variable sum_a : integer := 0;

variable sum_b : integer := 0;

variable contents_I1: integer;

variable allcycles : integer := 0;

variable i : integer;

variable n : integer;

variable n1 : integer;

constant nrofcycle_perinterval: integer :=25;

constant nrofinterval: integer :=18;

constant nrofallcycle_max: integer :=nrofcycle_perinterval*nrofinterval;

type input_values1 is array(0 to 25) of integer;

variable input_values: input_values1;

type amplitudearray1 is array(0 to 905) of integer;

variable contents_values: amplitudearray1;

variable y: amplitudearray1;

type interval_values1 is array(0 to 18) of integer;

function process1 (values: integer) return integer;

function increment_cycle return integer;

function contents_process(content:integer) return integer;

function increment_allcycle return integer;

function subfromallcycle(a: integer) return integer;

end package share;

library ieee;

use IEEE.std_logic_1164.all;

use work.share.all;

entity preamble_det is

Port(clk: in std_logic;

amplitudearray: in amplitudearray1;

interval_values: out interval_values1);

end preamble_det;

architecture behave of preamble_det is

function process1 (values: integer) return integer is

begin

cycle:=increment_cycle;

nrofcycle:=nrofcycle+1;

sum_a:=sum_a+values;

if (nrofcycle>nrofcycle_perinterval) then

sum_b:=sum_b+input_values(cycle);

contents_I1:=sum_a-sum_b;

contents_process(contents_I1);

end if;

input_values(cycle):=values;

end process1;

function increment_cycle return integer is

begin

if ((cycle+1) > nrofcycle_perinterval) then

return 1;

else

return cycle+1;

end if;

end increment_cycle;

function contents_process(contents_I1:integer) return integer is

begin

allcycles:=increment_allcycle;

contents_values (allcycles):=contents_I1;

if(nrofcycle>nrofallcycle_max) then

for n1 in 1 to 18 loop

i:=subfromallcycle(nrofcycle_perinterval*(n1-1));

interval_values (n1) := contents_values (i);

end loop;

end if;

end contents_process;

function increment_allcycle return integer is

begin

if ((allcycles+1) > nrofallcycle_max) then

return 1;

else

return (allcycles+1);

end if;

end increment_allcycle;

function subfromallcycle(a: integer) return integer is

begin

if ((allcycles-a)<1) then

return (allcycles-a+nrofallcycle_max);

else

return allcycles-a;

end if;

end subfromallcycle;

begin

process(clk)

begin

if (rising_edge(clk)) then

for n in 1 to 906 loop

y:= process1 (amplitudearray(n));

end loop;

end if;

end process;

end behave;

Then, I get following errors::

Error (10511): VHDL Qualified Expression error at preamble.vhd(60): contents_process type specified in Qualified Expression must match void type that is implied for expression by context

Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 1 warning

Error: Peak virtual memory: 275 megabytes

Error: Processing ended: Wed Sep 05 11:15:02 2012

Error: Elapsed time: 00:00:02

Error: Total CPU time (on all processors): 00:00:01

Could you please help me to correct it?

The syntax error is only the first of a huge number of syntax and semantic errors. I suppose they can be fixed somehow, but the new design doesn't change anything to the problem addressed in my previous post.

The first error says, you must not call a function without assigning the result to an object of correct type.

Hi, Thanks for the reply.

could you please recommend any good VHDL text book or anything else where I can understand such concepts.

your coding style still follows software programming style very much. other than just learning VHDL syntax, you got to forget about writing it similar to software coding style like C, C++, et c. honestly, you don't really need to get a good VHDL text book, just google them and you get tonnes of info.

what you might need is the book in digital logic/system design.

Hi, can anybody give some alternative way of writing array of array in VHDL having lets say 200 elements and each element consists of 14 bits .

The one I know is:

type elements is array(13 down to 0) of bit;

type array_elements is array( o to 200) of elements;

Although analysis and synthesis is succesful in Quartus

but give following errors for "Cyclone IVE" during compilation ::

Error (169281): There are 2817 IO input pads in the design, but only 281 IO input pad locations available on the device.

Error (169282): There are 2814 IO output pads in the design, but only 266 IO output pad locations available on the device.

oh, you just tied your array to I/Os...

You have to declare them as internal signals like this:

type elements is array (0 to 200) of std_logic_vector(13 downto 0);

signal bus_name : elements;

you gotta buck up your vhdl and the Quartus II basics too.

The program below compile with quartus ii for cyclone IVE.

but for confirmation: does it transfer 906 samples of 14 bit data from input to output as soon as significant bit is detected??

library ieee;

use ieee.std_logic_1164.all;

entity preamble_det is

port( clk: in std_logic;

detection: out std_logic;

input: in std_logic_vector(13 downto 0);

output: out std_logic_vector(13 downto 0));

end preamble_det;

architecture behave of preamble_det is

type bit_bus is array(905 downto 0) of std_logic_vector(13 downto 0);

signal element : bit_bus;

begin

transfer_data: process (clk) --transfer data at each clock

begin

if (clk'event and clk= '1') then

for i in 13 downto 8 loop

if(input(i) = '1') then

detection <= '1'; --significant bit detection

else

exit;

end if;

end loop;

for n in 905 downto 0 loop

element(n)<= input;

output<=element(n);

end loop;

end if;

end process transfer_data;

end behave;

one additional query: can we call a process using label from other process like function if we have multiple processes??