Detecting preamble

Picking a small snippet of your code

for n in 1 to 905 loop 
if ((cycle+1) > nrofcycle_perinterval) then
cycle:= 1;
else
cycle:=cycle+1;
end if; 
nrofcycle:=nrofcycle+1;
sum_a:=sum_a+(amplitudearray(n));

Do you understand what a VHDL iteration (e.g. a for loop) does? It constructs parallel logic. You have several unconstraint integer (32-bit each) arithmetic expressions inside the loop, as rough estimation the loop will consume at least several 100k logic cells. Can you imagine that Quartus doesn't like it? In any case, the design won't fit any reasonable FPGA size.

Simple conclusion, consider what you want to achieve, redesign your code to execute sequentially or find a different way to make it FPGA compatible.