Detecting preamble

The program below compile with quartus ii for cyclone IVE.

but for confirmation: does it transfer 906 samples of 14 bit data from input to output as soon as significant bit is detected??

library ieee;

use ieee.std_logic_1164.all;

entity preamble_det is

port( clk: in std_logic;

detection: out std_logic;

input: in std_logic_vector(13 downto 0);

output: out std_logic_vector(13 downto 0));

end preamble_det;

architecture behave of preamble_det is

type bit_bus is array(905 downto 0) of std_logic_vector(13 downto 0);

signal element : bit_bus;

begin

transfer_data: process (clk) --transfer data at each clock

begin

if (clk'event and clk= '1') then

for i in 13 downto 8 loop

if(input(i) = '1') then

detection <= '1'; --significant bit detection

else

exit;

end if;

end loop;

for n in 905 downto 0 loop

element(n)<= input;

output<=element(n);

end loop;

end if;

end process transfer_data;

end behave;

one additional query: can we call a process using label from other process like function if we have multiple processes??