Detecting preamble

Thanks for giving me a direction. As per your suggestion I used a Process as follows:

library ieee;

use ieee.std_logic_1164.all;

--declaring global variables

package share is

type input_values1 is array(0 to 25) of integer;

type amplitudearray1 is array(0 to 905) of integer;

type interval_values1 is array(0 to 18) of integer;

end package share;

library ieee;

use IEEE.std_logic_1164.all;

use work.share.all;

entity preamble_det is

Port(clk: in std_logic;

amplitudearray: in amplitudearray1;

interval_values: out interval_values1);

end preamble_det;

architecture behave of preamble_det is

constant nrofcycle_perinterval: integer :=25;

constant nrofinterval: integer :=18;

constant nrofallcycle_max: integer :=nrofcycle_perinterval*nrofinterval;

begin

process(clk)

variable contents_values: amplitudearray1;

variable input_values: input_values1;

variable n : integer;

variable n1 : integer;

variable nrofcycle : integer := 0;

variable cycle : integer := 0;

variable sum_a : integer := 0;

variable sum_b : integer := 0;

variable contents_I1 : integer;

variable allcycles : integer := 0;

variable i : integer;

begin

if (rising_edge(clk)) then

for n in 1 to 905 loop

if ((cycle+1) > nrofcycle_perinterval) then

cycle:= 1;

else

cycle:=cycle+1;

end if;

nrofcycle:=nrofcycle+1;

sum_a:=sum_a+(amplitudearray(n));

if (nrofcycle>nrofcycle_perinterval) then

sum_b:=sum_b+input_values(cycle);

contents_I1:=sum_a-sum_b;

if ((allcycles+1) > nrofallcycle_max) then

allcycles:= 1;

else

allcycles:= (allcycles+1);

end if;

contents_values (allcycles):=contents_I1;

if(nrofcycle>nrofallcycle_max) then

for n1 in 1 to 18 loop

if ((allcycles-(nrofcycle_perinterval*(n1-1)))<1) then

i:= (allcycles-(nrofcycle_perinterval*(n1-1))+nrofallcycle_max);

else

i:= allcycles-(nrofcycle_perinterval*(n1-1));

end if;

interval_values (n1) <= contents_values (i);

end loop;

end if;

end if;

input_values(cycle):=amplitudearray(n);

end loop;

end if;

end process;

end behave;

During running this program either Quartus II 11.0 becomes hang or I got the following errors::

Error: Out of memory in module quartus_map.exe (4097 megabytes used) while running 32-bit Quartus II on a 64-bit OS platform. Please use the 64-bit Quartus II to increase memory capacity.

Error: Current module quartus_map ended unexpectedly

Is there any way to reduce the memory? I checked the same Program in "C programming" where it works fine using 5 functions for each stage.

I read that ""Signal represents interconnection wires that connect component

instantiation ports together whereas Variable is used for local storage of temporary data and visible only inside a process"". But here I am still unable to decide which one I should take as a variable and which one as signal.

Further help will be highly appreciated.