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Altera_Forum's avatar
Altera_Forum
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13 years ago

Detecting preamble

Hello, I am trying to write a program to detect preamble of the attached signal. I am getting "error 10500:VHDL syntax error" for following code in Quartus. Can anyone correct me? As I am new to VHDL, I am unable to find it :cry:

Thanks in advance

Note: we are interested in only 8 bit preamble and 2 bit data (not whole 112 bit data).

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

package preamble is

constant NROF_CYCLES_per_interval: integer :=25;

constant NROF_INTERVALS: integer :=18;

constant NROF_ALL_CYCLES_MAX: integer :=NROF_CYCLES_per_interval*NROF_INTERVALS;

Variable cycle, all_cycles, nrof_cycles: integer :=0;

type Input_values is ARRAY (nrof_cycles) of integer;

function increment_cycle return integer;

function process1 (valu :integer) return integer;

function increment_all_cycles return integer;

function add_to_all_cycles (a: integer) return integer;

function contents_process(contents: integer) return integer;

end preamble;

package body preamble is

function increment_cycle

return integer is

begin

if (cycle +1 > nrof_cycles) then

return 1;

else

return cycle+1;

end if;

end increment_cycle;

function process1 (values: integer)

return integer is

variable myinput_values : input_values;

Variable SUM_A,SUM_B: integer :=0;

begin

cycle:=increment_cycle;

nrof_cycle:=nrof_cycle+1;

SUM_A:=SUM_A+values;

if(nrof_cycles> NROF_CYCLES_per_interval) then

SUM_B :=SUM_B + myinput_values[cycle];

contents_I1:=SUM_A-SUM_B;

contents_process(contents_I1);

end if;

myinput_values[cycle]:= values;

end process1;

function increment_all_cycles

return integer is

begin

if (all_cycles +1 > NROF_ALL_CYCLES_MAX) then

return 1;

else

return all_cycles+1;

end if;

end increment_all_cycles;

function add_to_all_cycles (a: integer)

return integer is

begin

if (all_cycles –a<1) then

return (all_cycles-a + NROF_ALL_CYCLES_MAX);

else

return all_cycles-a;

end if;

end add_to_all_cycles;

function contents_process(contents: integer)

return integer is

begin

all_cycles:=increment_all_cycles;

Contents_values[(all_cycles):=contents;

if (nrof_cycles>NROF_ALL_CYCLES_MAX) then

for i in 1 to 18 loop

Interval_values(i):=Contents_values(add_to_all_cycles (NROF_CYCLES*(I-1)));

end loop;

end if;

end contents_process

end preamble

Libraray IEEE;

Use IEEE.std_logic_1164.all;

Use work.preamble.all

Entity preamble_det is

Port(cycle: in std_logic;

values: in std_logic;

contents_I1: out std_logic;

Interval_values : out Input_values;

);

End preamble_det

Architcture behave of preamble_det is

Begin

end behave;

11 Replies

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I don't think your code does what you wanted it to do.

    Remember that all the lines in the "if (clk'event and clk= '1')" will be executed within the same clock cycle. So basically, at each clock cycle the 906 elements of your array are all filled with the same value: the input vector at the rising edge. 

    output<=element(n);
    This line is also executed 906 times, so the first 905 ones will be ignored and output will simply be fed with the value element(905), which is the value of input on the previous rising edge. You created a two cycle delay, and Quartus will optimize it by removing the first 905 of your array, which are useless. 

    detection <= '1'; --significant bit detection
    detection is never set to 0 anywhere in your code. It will start at an undefined value at power up (I'm not sure Quartus will set it to 0, but it doesn't need to do this to be compliant with the VHDL specification) and once set to 1 it will never change back. If Quartus is smart enough it may decide to optimize you code by just setting detection at a fixed value of 1 (but I haven't tested this).

    --- Quote Start ---

    one additional query: can we call a process using label from other process like function if we have multiple processes??

    --- Quote End ---

    you can't "call" a process, a process is a piece of hardware that is always there. You can use functions and procedures, but even there when you use them it isn't a "call" as you understand it in software, it is an instantiation. Each "call" will generate a new piece of hardware.

    As other replies suggested, you should start with a book about logic design and VHDL. Some people gave some good references on this forum, a search will probably help.