Detecting preamble

Hello FvM,

I tried different way using Functions as follows::

library ieee;

use ieee.std_logic_1164.all;

--making global variables as these variables are used by 5 functions in my case

package share is

variable nrofcycle : integer := 0;

variable cycle : integer := 0;

variable sum_a : integer := 0;

variable sum_b : integer := 0;

variable contents_I1: integer;

variable allcycles : integer := 0;

variable i : integer;

variable n : integer;

variable n1 : integer;

constant nrofcycle_perinterval: integer :=25;

constant nrofinterval: integer :=18;

constant nrofallcycle_max: integer :=nrofcycle_perinterval*nrofinterval;

type input_values1 is array(0 to 25) of integer;

variable input_values: input_values1;

type amplitudearray1 is array(0 to 905) of integer;

variable contents_values: amplitudearray1;

variable y: amplitudearray1;

type interval_values1 is array(0 to 18) of integer;

function process1 (values: integer) return integer;

function increment_cycle return integer;

function contents_process(content:integer) return integer;

function increment_allcycle return integer;

function subfromallcycle(a: integer) return integer;

end package share;

library ieee;

use IEEE.std_logic_1164.all;

use work.share.all;

entity preamble_det is

Port(clk: in std_logic;

amplitudearray: in amplitudearray1;

interval_values: out interval_values1);

end preamble_det;

architecture behave of preamble_det is

function process1 (values: integer) return integer is

begin

cycle:=increment_cycle;

nrofcycle:=nrofcycle+1;

sum_a:=sum_a+values;

if (nrofcycle>nrofcycle_perinterval) then

sum_b:=sum_b+input_values(cycle);

contents_I1:=sum_a-sum_b;

contents_process(contents_I1);

end if;

input_values(cycle):=values;

end process1;

function increment_cycle return integer is

begin

if ((cycle+1) > nrofcycle_perinterval) then

return 1;

else

return cycle+1;

end if;

end increment_cycle;

function contents_process(contents_I1:integer) return integer is

begin

allcycles:=increment_allcycle;

contents_values (allcycles):=contents_I1;

if(nrofcycle>nrofallcycle_max) then

for n1 in 1 to 18 loop

i:=subfromallcycle(nrofcycle_perinterval*(n1-1));

interval_values (n1) := contents_values (i);

end loop;

end if;

end contents_process;

function increment_allcycle return integer is

begin

if ((allcycles+1) > nrofallcycle_max) then

return 1;

else

return (allcycles+1);

end if;

end increment_allcycle;

function subfromallcycle(a: integer) return integer is

begin

if ((allcycles-a)<1) then

return (allcycles-a+nrofallcycle_max);

else

return allcycles-a;

end if;

end subfromallcycle;

begin

process(clk)

begin

if (rising_edge(clk)) then

for n in 1 to 906 loop

y:= process1 (amplitudearray(n));

end loop;

end if;

end process;

end behave;

Then, I get following errors::

Error (10511): VHDL Qualified Expression error at preamble.vhd(60): contents_process type specified in Qualified Expression must match void type that is implied for expression by context

Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 1 warning

Error: Peak virtual memory: 275 megabytes

Error: Processing ended: Wed Sep 05 11:15:02 2012

Error: Elapsed time: 00:00:02

Error: Total CPU time (on all processors): 00:00:01

Could you please help me to correct it?