Detecting preamble

Hi, can anybody give some alternative way of writing array of array in VHDL having lets say 200 elements and each element consists of 14 bits .

The one I know is:

type elements is array(13 down to 0) of bit;

type array_elements is array( o to 200) of elements;

Although analysis and synthesis is succesful in Quartus

but give following errors for "Cyclone IVE" during compilation ::

Error (169281): There are 2817 IO input pads in the design, but only 281 IO input pad locations available on the device.

Error (169282): There are 2814 IO output pads in the design, but only 266 IO output pad locations available on the device.