Define internal signal as a base clock?

I have a problem performing timing analysis on a design. I'm using the Classic timing analyser.

Suppose I have a device which has many (low speed) inputs on seprate physical pins, and I need to be able to select any one of them to use as the clock for some downstream logic. The selection between them is made by an external CPU writing a register over a separate, high speed, synchronous interface.

The code the might look like this:

PROCESS (everything...)

BEGIN

IF clk_cpu'event AND clk_cpu = '1' THEN

IF addr = clk_mux_addr THEN

clk_mux_setting <= data;

END IF;

clk_logic <= clk_array (clk_mux_setting);

END PROCESS;

All the clocks in clk_array are asychronous to each other and to the CPU. I know I'll get glitches in clk_logic when the CPU changes settings and this is OK.

Further on I then have:

PROCESS (clk_logic, clk_cpu)

BEGIN

IF clk_logic'event AND clk_logic = '1' THEN

result <= (stuff);

END IF;

IF clk_cpu'event AND clk_cpu = '1' THEN

result_meta <= result;

result_cpu <= result_meta;

END IF;

END PROCESS;

ie. I'm double sampling the result to get it back into the clk_cpu domain, and have no expectation at all of any relationship between clk_cpu and clk_logic.

However...

When running the timing analysis, Quartus picks up on the fact that clk_logic does depend on clk_cpu, because it depends on clk_mux_setting. Moreover, this is quite a long path, so the fitter is wasting effort and my Fmax is greatly reduced. What I see in the report is a setup time violation between result and result_meta.

This is a false path, of course, and I could just specify cut_timing_path between these two registers. But, the real code is considerably more complex, and it would mean that the timing constraints are closely tied in with the workings of the process.

So, what I really want to do is insist that clk_logic be treated as a base clock - ie. as though it came in from an external pin, with its own Fmax and no implied relationship to any other clock.

Is this possible without actually routing it out to a physical pin and back in again through another pin?

17 Replies

Altera_Forum
Honored Contributor
18 years ago
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The timing analyser is - erroneously, I think - considering the shortest possible path through that divider and the longest possible, and coming to the conclusion that there's a skew problem. It doesn't seem to notice that, whatever the path through the divider, the source and destination registers are in fact driven off the exact same global signal.
--- Quote End ---

The timing analyzer is probably doing the correct analysis. If there is more than one possible path for the clock (for example, more than one possible selection for a clock mux), the timing analyzer has to assume that one path is in effect at the time of the launching edge and another path is in effect at the time of the latching edge. The shortest and longest paths will be used in whichever combination is appropriate for clock setup and for clock hold. Most designs care about the timing only when the same clock path is selected for both launching and latching edges, but you have to tell the timing analyzer that this is the case.

This is one of the areas where TimeQuest has an advantage over the Classic Timing Analyzer. TimeQuest makes the same conservative assumption as the Classic Timing Analyzer about there possibly being different clock paths selected at the times of the launching and latching edges, but the SDC commands used by TimeQuest give you lots of control to tell the analyzer how the design actually works.
Altera_Forum
Honored Contributor
18 years ago
I'm sure you're right; if the divider were indeed reprogrammed between launch and latch edges then the paths it's using would indeed be correct. I'm 99% sure that I have 'Cut Timing Path' assignments on the register that controls the divider too, though.

I did have a play with TimeQuest yesterday, but what put me off was the need to edit the SDC file by hand; whilst I've no doubt that many designers are familiar with setting constraints in this way from other tools, I'm not. (I don't think I've read a manual in 10 years... seems a shame to have to start now!!)
Altera_Forum
Honored Contributor
18 years ago
--- Quote Start ---
I did have a play with TimeQuest yesterday, but what put me off was the need to edit the SDC file by hand...
--- Quote End ---

Once you have your initial SDC file, you do need to edit it to make changes. (Don't make the mistake some people do of making changes in the TimeQuest GUI and thinking write_sdc will then update their original SDC file with the changes. That's not the correct use of write_sdc.)

You still have GUI assistance for SDC changes. If you use the text editor, use "Edit --> Insert Constraint" to get to dialog boxes that will create the SDC commands and place them in the file. If you are editing a constraint that is already in the file, hover the mouse over the SDC command name to get a tooltip with a list of arguments. If you create constraints in the TimeQuest GUI, then copy them from the Console or History tab of the Console window to your SDC file after you are satisfied with them.
Altera_Forum
Honored Contributor
18 years ago
Could it be an option to synchronize divided clock to respective input clock, having only one clock path from input. The clock divider control path should be cut anyway.
Altera_Forum
Honored Contributor
17 years ago
I filed a service request asking that both on-line solutions found by Frank be checked for correctness (see post# 8 in this thread from FvM). Neither one is available now. I suspect they were removed because of my service request. I think the one for a 4-to-1 multiplexer was incorrect, and the one for FLEX devices needed to be updated for all relevant device families.
Altera_Forum
Honored Contributor
17 years ago
I guess maybe an update is in order...

I did eventually get to the bottom of things. There's no need to use TimeQuest - and in fact, I doubt it would solve the problem.

In my design, I have a bank of clocks, each of which can be sourced from numerous places under the control of a set of registers. One of these registers was getting optimised out - in name, at least - during synthesis, so the 'cut timing path' assignment associated with it was getting ignored.

So, the problem - and it's one that's caused me no end of grief in simulation too - is that during synthesis, not all the net names specified in the design are preserved. For example, if I have two components, joined together at the top level, then a signal will have at least three aliases: its name at the source (ie. the original assignment, in one component), another name at the top level, and another where it's an input to the second component.

So, assignments made to the top level signal name, or inputs to the second component, get lost and ignored. Worse still is that the name a signal does get in the netlist isn't necessarily one from my own source files at all, but from an inferred Altera library - so there's no way to even know what a net will end up called until after synthesis is complete and the result can be analysed.
Altera_Forum
Honored Contributor
17 years ago
Your complaints are common. The general guidance is to use register names instead of combinational node names where possible in assignments, to use "preserve" for registers and "keep" for combinational nodes in HDL synthesis attributes for nodes you want to be sure are available for assignments or simulation, and to use wildcards that often allow you to use names taken from the RTL (unless it is a node inside a megafunction or other IP block) with the wildcards representing the portions of the names that are created by Quartus (being careful not to create false matches with the wildcards). The node name used by Quartus will always be the name associated with the driver of the node unless you are using the get_pins collection in TimeQuest (and maybe for the Quartus native simulator--don't remember about that).

In the Node Finder, I am usually able to find the names I want and use them successfully in assignments if I use the "Design Entry (all names)" filter. I sometimes use a filter for just pins or just registers for convenience. Once in a great while it is necessary to use a particular filter like "Post-synthesis" or "Post-Compilation" to get the name needed by an assignment, or I have to be careful because a register and a combinational node have very similar names.

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Define internal signal as a base clock?

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