Define internal signal as a base clock?

I guess maybe an update is in order...

I did eventually get to the bottom of things. There's no need to use TimeQuest - and in fact, I doubt it would solve the problem.

In my design, I have a bank of clocks, each of which can be sourced from numerous places under the control of a set of registers. One of these registers was getting optimised out - in name, at least - during synthesis, so the 'cut timing path' assignment associated with it was getting ignored.

So, the problem - and it's one that's caused me no end of grief in simulation too - is that during synthesis, not all the net names specified in the design are preserved. For example, if I have two components, joined together at the top level, then a signal will have at least three aliases: its name at the source (ie. the original assignment, in one component), another name at the top level, and another where it's an input to the second component.

So, assignments made to the top level signal name, or inputs to the second component, get lost and ignored. Worse still is that the name a signal does get in the netlist isn't necessarily one from my own source files at all, but from an inferred Altera library - so there's no way to even know what a net will end up called until after synthesis is complete and the result can be analysed.