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Altera_Forum's avatar
Altera_Forum
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18 years ago

Define internal signal as a base clock?

I have a problem performing timing analysis on a design. I'm using the Classic timing analyser. Suppose I have a device which has many (low speed) inputs on seprate physical pins, and I need to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Could it be an option to synchronize divided clock to respective input clock, having only one clock path from input. The clock divider control path should be cut anyway.