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The timing analyser is - erroneously, I think - considering the shortest possible path through that divider and the longest possible, and coming to the conclusion that there's a skew problem. It doesn't seem to notice that, whatever the path through the divider, the source and destination registers are in fact driven off the exact same global signal.
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The timing analyzer is probably doing the correct analysis. If there is more than one possible path for the clock (for example, more than one possible selection for a clock mux), the timing analyzer has to assume that one path is in effect at the time of the launching edge and another path is in effect at the time of the latching edge. The shortest and longest paths will be used in whichever combination is appropriate for clock setup and for clock hold. Most designs care about the timing only when the same clock path is selected for both launching and latching edges, but you have to tell the timing analyzer that this is the case.
This is one of the areas where TimeQuest has an advantage over the Classic Timing Analyzer. TimeQuest makes the same conservative assumption as the Classic Timing Analyzer about there possibly being different clock paths selected at the times of the launching and latching edges, but the SDC commands used by TimeQuest give you lots of control to tell the analyzer how the design actually works.
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