Define internal signal as a base clock?

Your complaints are common. The general guidance is to use register names instead of combinational node names where possible in assignments, to use "preserve" for registers and "keep" for combinational nodes in HDL synthesis attributes for nodes you want to be sure are available for assignments or simulation, and to use wildcards that often allow you to use names taken from the RTL (unless it is a node inside a megafunction or other IP block) with the wildcards representing the portions of the names that are created by Quartus (being careful not to create false matches with the wildcards). The node name used by Quartus will always be the name associated with the driver of the node unless you are using the get_pins collection in TimeQuest (and maybe for the Quartus native simulator--don't remember about that).

In the Node Finder, I am usually able to find the names I want and use them successfully in assignments if I use the "Design Entry (all names)" filter. I sometimes use a filter for just pins or just registers for convenience. Once in a great while it is necessary to use a particular filter like "Post-synthesis" or "Post-Compilation" to get the name needed by an assignment, or I have to be careful because a register and a combinational node have very similar names.