Define internal signal as a base clock?

I'm sure you're right; if the divider were indeed reprogrammed between launch and latch edges then the paths it's using would indeed be correct. I'm 99% sure that I have 'Cut Timing Path' assignments on the register that controls the divider too, though.

I did have a play with TimeQuest yesterday, but what put me off was the need to edit the SDC file by hand; whilst I've no doubt that many designers are familiar with setting constraints in this way from other tools, I'm not. (I don't think I've read a manual in 10 years... seems a shame to have to start now!!)