DAC with THDB-ADA on DE2-115

Hi !

I'm currently working with DE2-70 and the daughter board THBD-ADA, but by a different way : I have to send a sinus wave (in digital) from the board to the DAC converter, then to the ADC converter, and get it back, to study this transmission. For being able to see the signals, i'm using SignalTap, but i don't know if my signals are sent or not received...

I've already tried to use the code you've purposed, and adapt it, but it doesn't works..

This is my code :

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all; -- WARP : use work.std_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_signed.all;

use ieee.numeric_std.all;

ENTITY Coucou Is

PORT( iCLK_50 : IN std_logic; -- Horloge de 50 MHz

-- Entrees/Sorties

DAC_DA, DAC_DB : OUT std_logic_vector(13 downto 0); -- D-A

ADC_DA, ADC_DB : IN std_logic_vector(13 downto 0); -- A-D

-- Setup ADC and DAC

DAC_MODE : OUT std_logic; -- DAC mode, 1 for dual, 0 for interleaved

DAC_WRTA : OUT std_logic; -- Write signal Channel A

DAC_WRTB : OUT std_logic; -- Write signal Channel B

ADC_OEA : OUT std_logic; -- Channel A enable

ADC_OEB : OUT std_logic; -- Channel b enable

PLL_OUT_ADC0, PLL_OUT_ADC1 : OUT std_logic;

PLL_OUT_DAC0, PLL_OUT_DAC1 : OUT std_logic); -- Clock from GPIO

END Coucou;

ARCHITECTURE Archi_Coucou OF Coucou IS

TYPE VAL_FUNCTION IS ARRAY (0 TO 49) OF INTEGER; -- tableau de 50 entiers

SIGNAL Sinus : VAL_FUNCTION;

SIGNAL a : INTEGER;

SIGNAL clockF, clockR : std_logic;

BEGIN

--Create signal------------------------------

Sinus <= (0 => 0, 1 => 1027, 2 => 2037, 3 => 3016, 4 => 3947,

5 => 4815, 6 => 5608, 7 => 6312, 8 => 6917, 9 => 7412,

10 => 7791, 11 => 8047, 12 => 8176, 13 => 8176, 14 => 8047, -- 50 points per periode

15 => 7791, 16 => 7412, 17 => 6917, 18 => 6312, 19 => 5608,

20 => 4815, 21 => 3947, 22 => 3016, 23 => 2037, 24 => 1027, -- Frequency of 10 MHz

25 => 0, 26 => -1027, 27 => -2037, 28 => -3016, 29 => -3947,

30 => -4815, 31 => -5608, 32 => -6312, 33 => -6917, 34 => -7412, -- points calculated for 14-bit words

35 => -7791, 36 => -8047, 37 => -8176, 38 => -8176, 39 => -8047,

40 => -7791, 41 => -7412, 42 => -6917, 43 => -6312, 44 => -5608,

45 => -4815, 46 => -3947, 47 => -3016, 48 => -2037, 49 => -1027);

--Clock processing---------------------------

process(iCLK_50)

begin

if falling_edge(iCLK_50) then

clockF <= not(clockF);

end if;

if rising_edge(iCLK_50) then

clockR <= not(clockR);

end if;

end process;

--DAC and ADC interface----------------------

PLL_OUT_ADC0 <= clockR;

PLL_OUT_ADC1 <= clockR;

PLL_OUT_DAC0 <= clockF;

PLL_OUT_DAC1 <= clockF;

DAC_WRTA <= clockF;

DAC_WRTB <= clockF;

DAC_MODE <= '1'; -- Dual mode

ADC_OEA <= '0';

ADC_OEB <= '1';

-- Outputs

create_signal_process: process(clockR)

VARIABLE CLK_Count : INTEGER :=0;

begin

if rising_edge(clockR) then

IF (CLK_Count < 50) THEN

a <= Sinus (CLK_Count);

DAC_DB <= std_logic_vector(to_signed(a, 14)); -- Convert sinus into 14-bit word

CLK_Count := CLK_Count + 1;

ELSE

CLK_Count := 0;

END IF;

end if;

end process;

END Archi_Coucou;

Does somebody can help me ?

Thanks and scuse me for my approximative english ...

Hi LouisMig,

I don't see anything wrong with the code except a minor mistake about using the library. These library should not be together

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

or

use ieee.std_logic_arith.all;

use ieee.std_logic_signed.all;

or

use ieee.numeric_std.all;

I don't know what will happen if you will use them together like that. In our code, you should include these:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

As I'm a bit hungry, I will eat something now :D But I wanna check if your simulated signal is correct, so can you show me the testbench simulation of the code with these signal:

DAC_DB (in binary) and clockR?

One more thing, are your sure the pins assignment for your DE0-70 is correct?

Thanks for your quick answer !

I've changed the librairies, thank you, I did not know how to use them ^^

More over i've checked the pin assignement, it seems good..

This is my simulation, and below the setup. However I don't understand why clockF and clockR are in phase...

https://www.alteraforum.com/forum/attachment.php?attachmentid=8720

And i've forgetten to say : I'va connected the DA-Channel B with the AD-Channel B by a SMA wire.

That's why it doesn't work I think. You have disabled ADC channel B already:

ADC_OEB <= '1'; this pis is active low, should be 0.

Can you make another change to your code, this:

SIGNAL clockF, clockR : std_logic;

to this:

SIGNAL clockF, clockR : std_logic := '0';

and display the iCLK_50 in your simulation

I've done the modification, but it is still the same result for the simulation.

And I can't display the iCLK_50, because it is impossible to define a signal as both clock signal and SignalTap signal ...

Hi Dear Tan,

I just bought the THDB ADA to be use with DE2-115 board. for the 1st timer I tried to feed the device a function from function generator, and display it on an oscilloscope. I think I got all the pin assignment which I did acknowledge. But it seems that there's none function displayed on the output display. What am I missing in the code ? what do i do ? I think some of your line below wont be necessary for mine right ?

--PLL_OUT_ADC(0) <= clockR;

--PLL_OUT_ADC(1) <= clockR;

--PLL_OUT_DAC(0) <= clockF;

--PLL_OUT_DAC(1) <= clockF;

--DAC_WRTA <= clockF;

--DAC_WRTB <= clockF;

What is that PLL_OUT_xxx & DAC_WRTA/B is for ?

---------------------------------------------------------------------------------------------

Following is my code in VHDL

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY SIN IS

PORT (

-- ADC / DAC ---------------------

ADC_DB : IN STD_LOGIC_VECTOR(13 DOWNTO 0);

DAC_DB : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);

-- Setup ADC and DAC -------------

DAC_MODE : out std_logic; -- DAC mode, 1 for dual

--DAC_WRTA : out std_logic; -- Write signal Channel A

--DAC_WRTB : out std_logic; -- Write signal Channel B

ADC_OEA : out std_logic; -- Channel A enable

ADC_OEB : out std_logic -- Channel b enable

--PLL_OUT_ADC : out std_logic_vector(1 downto 0);

--PLL_OUT_DAC : out std_logic_vector(1 downto 0) -- Clock from HSMC

-- Clock -------------------------

--CLOCK_50 : IN std_logic

&nbsp;);

END SIN;

ARCHITECTURE dataflow OF SIN IS

BEGIN

--Clock processing---------------------------

--process(CLOCK_50)

--begin

-- if falling_edge(CLOCK_50) then

-- clockF <= not(clockF);

-- end if;

-- if rising_edge(CLOCK_50) then

-- clockR <= not(clockR);

-- end if;

--end process;

--DAC and ADC interface----------------------

--PLL_OUT_ADC(0) <= clockR;

--PLL_OUT_ADC(1) <= clockR;

--PLL_OUT_DAC(0) <= clockF;

--PLL_OUT_DAC(1) <= clockF;

--DAC_WRTA <= clockF;

--DAC_WRTB <= clockF;

DAC_MODE <= '1'; -- Dual mode

ADC_OEA <= '0';

ADC_OEB <= '0';

--Original Plan----------------------------

DAC_DB<=ADC_DB;

END dataflow;

Hi Roy,

I'm sorry for the dela as I was travelling for the holiday.

What you need is exactly my code. The PLLs are the clock from FPGA board to the daughterboard. The WRT is, to be simple, to enable the write command to write to DAC

Cheers,

Tan

I used clockR/F to avoid clock skew. You can use:

ClockR<=Clock;

ClockF<=not(Clock);

--- Quote Start ---

Hi there,

I'm working with DAC on the daughter board THDB-ADA. The pin assignments are correct, I believe, but the circuit doesn't seem to be working.

Here are my waveforms from ModelSim, can somebody give me some suggestion on what I did wrong?

http://www.alteraforum.com/forum/attachment.php?attachmentid=6876&stc=1

fyi: I create the data output to the board from 0-16300-0... (so that it will be a triangle waveform)

I'm still doing and glad to here from you.

Thank you,

Tan

--- Quote End ---

I am sorry , i am very very new to DE2-115 , now i need to connect my DE2-115 to THDB-ADA_HSMC , same like yours . But can i know is there any extra coding needed in order to make the connection ? And also how do you assign the pin assignment for this ADA?