DAC with THDB-ADA on DE2-115

Hi Dear Tan,

I just bought the THDB ADA to be use with DE2-115 board. for the 1st timer I tried to feed the device a function from function generator, and display it on an oscilloscope. I think I got all the pin assignment which I did acknowledge. But it seems that there's none function displayed on the output display. What am I missing in the code ? what do i do ? I think some of your line below wont be necessary for mine right ?

--PLL_OUT_ADC(0) <= clockR;

--PLL_OUT_ADC(1) <= clockR;

--PLL_OUT_DAC(0) <= clockF;

--PLL_OUT_DAC(1) <= clockF;

--DAC_WRTA <= clockF;

--DAC_WRTB <= clockF;

What is that PLL_OUT_xxx & DAC_WRTA/B is for ?

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Following is my code in VHDL

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY SIN IS

PORT (

-- ADC / DAC ---------------------

ADC_DB : IN STD_LOGIC_VECTOR(13 DOWNTO 0);

DAC_DB : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);

-- Setup ADC and DAC -------------

DAC_MODE : out std_logic; -- DAC mode, 1 for dual

--DAC_WRTA : out std_logic; -- Write signal Channel A

--DAC_WRTB : out std_logic; -- Write signal Channel B

ADC_OEA : out std_logic; -- Channel A enable

ADC_OEB : out std_logic -- Channel b enable

--PLL_OUT_ADC : out std_logic_vector(1 downto 0);

--PLL_OUT_DAC : out std_logic_vector(1 downto 0) -- Clock from HSMC

-- Clock -------------------------

--CLOCK_50 : IN std_logic

&nbsp;);

END SIN;

ARCHITECTURE dataflow OF SIN IS

BEGIN

--Clock processing---------------------------

--process(CLOCK_50)

--begin

-- if falling_edge(CLOCK_50) then

-- clockF <= not(clockF);

-- end if;

-- if rising_edge(CLOCK_50) then

-- clockR <= not(clockR);

-- end if;

--end process;

--DAC and ADC interface----------------------

--PLL_OUT_ADC(0) <= clockR;

--PLL_OUT_ADC(1) <= clockR;

--PLL_OUT_DAC(0) <= clockF;

--PLL_OUT_DAC(1) <= clockF;

--DAC_WRTA <= clockF;

--DAC_WRTB <= clockF;

DAC_MODE <= '1'; -- Dual mode

ADC_OEA <= '0';

ADC_OEB <= '0';

--Original Plan----------------------------

DAC_DB<=ADC_DB;

END dataflow;