DAC with THDB-ADA on DE2-115

Hi !

I'm currently working with DE2-70 and the daughter board THBD-ADA, but by a different way : I have to send a sinus wave (in digital) from the board to the DAC converter, then to the ADC converter, and get it back, to study this transmission. For being able to see the signals, i'm using SignalTap, but i don't know if my signals are sent or not received...

I've already tried to use the code you've purposed, and adapt it, but it doesn't works..

This is my code :

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all; -- WARP : use work.std_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_signed.all;

use ieee.numeric_std.all;

ENTITY Coucou Is

PORT( iCLK_50 : IN std_logic; -- Horloge de 50 MHz

-- Entrees/Sorties

DAC_DA, DAC_DB : OUT std_logic_vector(13 downto 0); -- D-A

ADC_DA, ADC_DB : IN std_logic_vector(13 downto 0); -- A-D

-- Setup ADC and DAC

DAC_MODE : OUT std_logic; -- DAC mode, 1 for dual, 0 for interleaved

DAC_WRTA : OUT std_logic; -- Write signal Channel A

DAC_WRTB : OUT std_logic; -- Write signal Channel B

ADC_OEA : OUT std_logic; -- Channel A enable

ADC_OEB : OUT std_logic; -- Channel b enable

PLL_OUT_ADC0, PLL_OUT_ADC1 : OUT std_logic;

PLL_OUT_DAC0, PLL_OUT_DAC1 : OUT std_logic); -- Clock from GPIO

END Coucou;

ARCHITECTURE Archi_Coucou OF Coucou IS

TYPE VAL_FUNCTION IS ARRAY (0 TO 49) OF INTEGER; -- tableau de 50 entiers

SIGNAL Sinus : VAL_FUNCTION;

SIGNAL a : INTEGER;

SIGNAL clockF, clockR : std_logic;

BEGIN

--Create signal------------------------------

Sinus <= (0 => 0, 1 => 1027, 2 => 2037, 3 => 3016, 4 => 3947,

5 => 4815, 6 => 5608, 7 => 6312, 8 => 6917, 9 => 7412,

10 => 7791, 11 => 8047, 12 => 8176, 13 => 8176, 14 => 8047, -- 50 points per periode

15 => 7791, 16 => 7412, 17 => 6917, 18 => 6312, 19 => 5608,

20 => 4815, 21 => 3947, 22 => 3016, 23 => 2037, 24 => 1027, -- Frequency of 10 MHz

25 => 0, 26 => -1027, 27 => -2037, 28 => -3016, 29 => -3947,

30 => -4815, 31 => -5608, 32 => -6312, 33 => -6917, 34 => -7412, -- points calculated for 14-bit words

35 => -7791, 36 => -8047, 37 => -8176, 38 => -8176, 39 => -8047,

40 => -7791, 41 => -7412, 42 => -6917, 43 => -6312, 44 => -5608,

45 => -4815, 46 => -3947, 47 => -3016, 48 => -2037, 49 => -1027);

--Clock processing---------------------------

process(iCLK_50)

begin

if falling_edge(iCLK_50) then

clockF <= not(clockF);

end if;

if rising_edge(iCLK_50) then

clockR <= not(clockR);

end if;

end process;

--DAC and ADC interface----------------------

PLL_OUT_ADC0 <= clockR;

PLL_OUT_ADC1 <= clockR;

PLL_OUT_DAC0 <= clockF;

PLL_OUT_DAC1 <= clockF;

DAC_WRTA <= clockF;

DAC_WRTB <= clockF;

DAC_MODE <= '1'; -- Dual mode

ADC_OEA <= '0';

ADC_OEB <= '1';

-- Outputs

create_signal_process: process(clockR)

VARIABLE CLK_Count : INTEGER :=0;

begin

if rising_edge(clockR) then

IF (CLK_Count < 50) THEN

a <= Sinus (CLK_Count);

DAC_DB <= std_logic_vector(to_signed(a, 14)); -- Convert sinus into 14-bit word

CLK_Count := CLK_Count + 1;

ELSE

CLK_Count := 0;

END IF;

end if;

end process;

END Archi_Coucou;

Does somebody can help me ?

Thanks and scuse me for my approximative english ...