Constrain I/O in TimeQuest for simple SPI interface (ADC)

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Hello all!

I have successfully constrained a base clock and a PLL generated clock in my design without any timing violations but I am still getting some unconstrained paths for my IOs I use for a Analog-toDigital Converter using an SPI interface. The problem is that I am not using the PLL clock to clock the outside chips but instead I create another clock much much slower.

My question is that since i am not clocking any registers in my design with this generated SPI clock, how do I constrain the IO port? Is it ok if I just constrain it as a false path so that my timing reports are complete or shall I do something else?

In case I need to do a false path then how do I do it in this case?

Thanks in advance

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You always need io constraints (never a false path) even at very slow clock rates since slow speed can not protect hold violations, even setup violation can occur if delays are not cared for.

I understand you are using gated slow clock for io registers then you need to define that clock and go from there.

In SPI the clock is a misnomer as it most often isn't a continuous clock but rather a limited number of 'strobes'. Usually it has a rather large period in comparison to the speed of the FPGA itself. As such the timing of the SPI-signals in respect to each other are (should be) correct 'by design' and you could use a false path for all the SPI signals (out and in) (and you'd get away scot free). Of course specifying a relaxed constraint doesn't hurt.

The false paths :

set_false_path -from * to {SPI_Clk SPI_SS SP_MoSi }
set_false_path -from SPI_MiSo to *

I assume here that you synchronise the incoming SPI_MiSo with the usual double register chain.

Thanks for the answers!

The thing is that the SPI clock is not used to clock any register on the FPGA. So why would I constrain this clock? The same applies to all I/O signals that are not clocks, why would i constrain them.

In general I do not understand the constraining of clocks that do not interact with internal fpga registers as well as constraining non-clock signals that are exported to the pins.

josyb: I didnt understand the double register chain.

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I didnt understand the double register chain.

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In case you read from the SPI, the SPI-MiSo signal will not be synchronous to the internal PLL clock you use to sample it. To avoid metastability issue we usually register the incoming signal with two (or more) successive registers(clocked by the internal clock). But, thinking about my original comment, the timing is 'correct by design' and when you sample this incoming signal it will be stable and meet all set-up and hold times.

Thanks!

The metastability issue is only for data coming as inputs to the pins?

Hello again!

Thanks a lot for your time. I have finished a generic SPI interface for an ADC plus a custom I2C interface, I now understand all the concepts of metastability, double register chain (synchronizers), false paths as well as 'correct by design'.