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Altera_Forum
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11 years ago

Constrain I/O in TimeQuest for simple SPI interface (ADC)

Hello all! I have successfully constrained a base clock and a PLL generated clock in my design without any timing violations but I am still getting some unconstrained paths for my IOs I use for...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hello again!

Thanks a lot for your time. I have finished a generic SPI interface for an ADC plus a custom I2C interface, I now understand all the concepts of metastability, double register chain (synchronizers), false paths as well as 'correct by design'.