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Hello all!
I have successfully constrained a base clock and a PLL generated clock in my design without any timing violations but I am still getting some unconstrained paths for my IOs I use for a Analog-toDigital Converter using an SPI interface. The problem is that I am not using the PLL clock to clock the outside chips but instead I create another clock much much slower.
My question is that since i am not clocking any registers in my design with this generated SPI clock, how do I constrain the IO port? Is it ok if I just constrain it as a false path so that my timing reports are complete or shall I do something else?
In case I need to do a false path then how do I do it in this case?
Thanks in advance
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You always need io constraints (never a false path) even at very slow clock rates since slow speed can not protect hold violations, even setup violation can occur if delays are not cared for.
I understand you are using gated slow clock for io registers then you need to define that clock and go from there.
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