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Altera_Forum
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11 years ago

Constrain I/O in TimeQuest for simple SPI interface (ADC)

Hello all! I have successfully constrained a base clock and a PLL generated clock in my design without any timing violations but I am still getting some unconstrained paths for my IOs I use for...
Altera_Forum's avatar
Altera_Forum
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11 years ago

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I didnt understand the double register chain.

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In case you read from the SPI, the SPI-MiSo signal will not be synchronous to the internal PLL clock you use to sample it. To avoid metastability issue we usually register the incoming signal with two (or more) successive registers(clocked by the internal clock). But, thinking about my original comment, the timing is 'correct by design' and when you sample this incoming signal it will be stable and meet all set-up and hold times.