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Altera_Forum
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11 years ago

Constrain I/O in TimeQuest for simple SPI interface (ADC)

Hello all! I have successfully constrained a base clock and a PLL generated clock in my design without any timing violations but I am still getting some unconstrained paths for my IOs I use for...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Thanks for the answers!

The thing is that the SPI clock is not used to clock any register on the FPGA. So why would I constrain this clock? The same applies to all I/O signals that are not clocks, why would i constrain them.

In general I do not understand the constraining of clocks that do not interact with internal fpga registers as well as constraining non-clock signals that are exported to the pins.

josyb: I didnt understand the double register chain.