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Altera_Forum
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11 years ago

Constrain I/O in TimeQuest for simple SPI interface (ADC)

Hello all! I have successfully constrained a base clock and a PLL generated clock in my design without any timing violations but I am still getting some unconstrained paths for my IOs I use for...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Yes, the metastability issue is only for inputs to the FPGA pins, and then only for those signals which are asynchronous to our internal clocks. With asynchronous we think of signals without any known relationship to the internal clock we use to sample it.