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Altera_Forum
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11 years ago

Constrain I/O in TimeQuest for simple SPI interface (ADC)

Hello all! I have successfully constrained a base clock and a PLL generated clock in my design without any timing violations but I am still getting some unconstrained paths for my IOs I use for...
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Altera_Forum
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11 years ago

In SPI the clock is a misnomer as it most often isn't a continuous clock but rather a limited number of 'strobes'. Usually it has a rather large period in comparison to the speed of the FPGA itself. As such the timing of the SPI-signals in respect to each other are (should be) correct 'by design' and you could use a false path for all the SPI signals (out and in) (and you'd get away scot free). Of course specifying a relaxed constraint doesn't hurt.

The false paths :

set_false_path -from * to {SPI_Clk SPI_SS SP_MoSi }
set_false_path -from SPI_MiSo to *

I assume here that you synchronise the incoming SPI_MiSo with the usual double register chain.