Clock groups ignored by Timing analyzer

Hi @sstrell ,

I just checked the Ignored SDC report on Timing Analyzer (under Constraint Diagnostics) and I see that my constraints are not ignored (at least not here). But I also checked the .sta.rpt file and I saw that there has been no exception between the two domains that I set by introducing the clock groups in my entry above. Here's one of the many entries I saw in that report:

Path #1: Setup slack is -9.497 (VIOLATED)
===============================================================================
+-----------------------------------------------------------------------------------------------------------------+
; Path Summary                                                                                                    ;
+---------------------------------+-------------------------------------------------------------------------------+
; Property                        ; Value                                                                         ;
+---------------------------------+-------------------------------------------------------------------------------+
; From Node                       ; i_max|rx_link_layer_1|rx_link_layer_1|cfg_output_switch                       ;
; To Node                         ; i_max|rx_link_layer_4|rx_link_layer_4|link_layer_fifo_showahead|s_p1_data[15] ;
; Launch Clock                    ; blk_clk_n_rst.i_pll_sys|iopll_0|outclk0                                       ;
; Latch Clock                     ; i_max|fpga_emif_ddr4|fpga_emif_ddr4_core_usr_clk                              ;
; SDC Exception                   ; No SDC Exception on Path                                                      ;
; Data Arrival Time               ; 4060.638                                                                      ;
; Data Required Time              ; 4051.141                                                                      ;
; Slack                           ; -9.497 (VIOLATED)                                                             ;
; Worst-Case Operating Conditions ; Slow 900mV 100C Model                                                         ;

So somehow my clock groups were ignored and the tool considers the timing between two domains. I also tried splitting the `set_clock_groups` command above in multiple `set_clock_groups` command where each command has only 2 different groups as it's stated by Intel here that the Set Clock Groups dialog box only permits two clock groups. However, it made no impact at all, I have the exact same issues at the end..

The target device is Arria 10 and I'm using the Quartus version 21.3 Pro. I attached my .sdc file here so that you can have a better sight on my constraints.

Could you specify the archive settings that you want ? I don't want to provide 'too less' files to you, but checking all boxes here generates gigabytes of data...

@TingJiangT_Intel Could you send me a link via email so that I can upload the archived project ? I tried all the options above and any option is greater than 71 MBytes, which is the limit I'm allowed to attach files here.

Hi,

My .sdc is correctly loaded into the project and there is no typos whatsoever, I directly copy-pasted the names from the Timing Analyzer. I tried defining false paths with the syntax you suggested, but the result is the same. No ignored constraints and no applied constraints for the false paths... And yes, I still get the timing violations at the clock domain crossings.

Not sure what you meant by "a detailed timing report", these should be the details I need to look for, right ?

I applied both "Superior performance with synthesis optimizations" and "Balanced" flows, the results are the same.

Thanks for the suggestions anyways !