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anonimcs's avatar
anonimcs
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2 years ago
Solved

Clock groups ignored by Timing analyzer

Hi all, I have a design with multiple clock domains. I want to ignore the timing checks for the paths where CDC happens. For this purpose, I have set clock groups in my sdc file, code can be found b...
Timing
  • anonimcs's avatar
    anonimcs
    2 years ago

    The issue was that the .sdc file was read before all the other .ip files are read in the .qsf file. When I moved the line to read the .sdc file after reading the .ip files, the issue is gone, and I can see false paths set in the report for clock transfers. This issue was also mentioned in this article here. In case the link becomes broken in the future, I attach a screenshot of the link content below.

TingJiangT_Intel's avatar
TingJiangT_Intel
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2 years ago

Just make sure that after restoring the timing analyzer can be opened without going through the synthesis process.

You can open the QAR file after archiving the project to verify this. Thanks.


  • anonimcs's avatar
    anonimcs
    Icon for Contributor rankContributor
    2 years ago

    @TingJiangT_Intel Could you send me a link via email so that I can upload the archived project ? I tried all the options above and any option is greater than 71 MBytes, which is the limit I'm allowed to attach files here.